![]() In above code,I have used for loop to increment index and assign next data bit,but index is not incrementing and data bits are not assigning.How do i rectify it?I wanna simulate it without test bench. Module trai1enc( din ,clk ,reset ,dout ) So output data length can vary from 0 bits to 15 bits. Length of output data is specified through reqlen (request length) input port. In this project we have a 32'bit parallel data input and a variable length serial data output. How to write the code for it without the testbench to simulate,So that data (serial input) should be continuously sent (maximum up to 4 bits i want to send). Variable length Parallel to Serial Converter. ![]() ![]() I have written serial in parallel out shift register verilog code. ![]()
0 Comments
Leave a Reply. |
AuthorWrite something about yourself. No need to be fancy, just an overview. Archives
December 2022
Categories |